Click here to read my paper.
This past summer, to quench my thirst for deeper knowledge in electrical engineering, I created a challenge for myself: examine, and try to improve the performance of phase locked loops.
Phase-locked loops are vital for almost all pieces of modern technology to run smoothly. They ensure that a device’s clock signal stays steady. Imagine your 8:30AM alarm goes off at 8:35AM instead, causing you to be late for work. Or, even worse, your alarm goes off at 8:25AM, forcing you to sacrifice five precious minutes of sleep, and throwing off your mood for the rest of the day.
While mobile phones and wifi routers don’t have clocks like we do, they use the same concept of a clock to make sure they complete their tasks at the right time.
My goal for ths summer was to create a simulatable model of a phase-locked loop, experiment with different parameters and observe the behavior, and document my findings to inspire methods of improvement.
I focused on testing two upgrades:
- Dual-loop design: I used one loop with a wide bandwidth to match with the signal quickly, and another with a narrow bandwidth to fine-tune the output. It’s like accelerating quickly once a traffic light turns green, then using more precise adjustments to maintain a certain speed.
- Dual-edge triggered phase frequency detector: This version reacts to both the rising and falling edges of the signal, instead of only reacting to the rising edge. This doubles the feedback rate and speeds up the system.
The results were clear: both methods cut down on overshoot and locked onto signals faster. The dual-edge phase-frequency detector locked in two cycles quicker, and the dual-loop design shaved off six cycles compared to the standard setup. Next, I plan to dive into digital enhancements, better testing methods, and fresh ideas to push performance even further.